This invention relates to a data processor for handling data in synchronization with an internal clock signal having a higher frequency than an applied external clock signal and for performing data transmission with an external device in synchronization with the external clock signal.
In the case that a slow external device, such as a memory and a coprocessor, is coupled to a data processor containing therein a fast central processing unit (CPU), a clock generation circuit is disposed in the data processor for generating from an external clock signal an internal clock signal having a frequency which is an integral multiple of the frequency of the external clock signal. The CPU executes data processing in synchronization with the internal clock signal and issues a data transmission request in synchronization with the internal clock signal; however, the transmission of data between the CPU and the external device must synchronize with the external clock signal.
External devices have their respective native setup times. For instance, it is not until a certain length of time elapses exceeding the setup time of an external device after an address signal that is applied to the external device is determined that data transmission is actually allowed to commence.
There have been demands for a fast data processor capable of guaranteeing the setup time of various external devices and of realizing data transmission with an external device in synchronization with an external clock signal. However, such demands have not been realized yet.